As the art of computer graphics has grown in sophistication, uses being made of computer graphics display systems have become increasingly various and creative. For example, in many modern applications, several display systems are employed at once to provide a larger viewing area than could be provided by a single display system operating alone. One such application is known popularly as a "virtual reality theater." In a typical virtual reality theater, multiple computer graphics display systems are used to project images on each of the walls of a room so that an observer within the room can see the images no matter in which direction he or she looks or moves. Often, the presentation of the images changes depending on the observer's position or orientation within the room as indicated by a tracking device. Other types of virtual reality theaters use multiple monitors oriented around a relatively stationary observer. The latter types of virtual reality theaters are frequently used, for example, in flight simulators.
Stereoscopic display techniques are also sometimes employed in computer graphics systems. In stereoscopic applications, left- and right-eye views or "channels" are sequentially and alternately displayed while special eyewear worn by the observer alternately occludes the observer's right and left channels of vision. When the eyewear and the display are synchronized properly, the observer's left eye always sees the left channel and the observer's right eye always sees the right channel. The effect for the observer is binocular stereopsis. In other words, the observer is given the experience of having depth perception while viewing the displayed scene.
If such a stereoscopic technique were to be employed in a multi-display system, then not only must all of the display devices in the system present the same channel (left or right) at the same time, but also the vertical refresh cycles should be synchronized so that all of the display devices in the system begin their vertical retrace at nearly the same time.
By way of background, a typical single-display computer graphics system 100 is shown in FIG. 1. CPU 102, system bus 104, system memory 106 and peripherals 108 represent any host computer system including a personal computer, workstation or mainframe. Display processor 110, frame buffer 112, video controller 114 and CRT monitor 116 represent a typical computer graphics "pipeline" 120 for displaying images generated by the host computer system. Pixel data representing an image are written into frame buffer 112 by display processor 110. (In lower-end systems, display processor 110 may not be present; in such lower-end systems, the host computer system writes pixel data into frame buffer 112 directly.) Video controller 114 reads pixel data from frame buffer 112, converts the pixel data into analog form, and drives CRT monitor 116 by generating appropriate horizontal and vertical timing signals and using the converted pixel data to determine R, G and B beam intensities. For stereoscopic applications, eyewear 118 is provided for alternately occluding the observer's eyes as previously described. Virtual reality theaters and other immersive environments are commonly constructed by using multiple instances of computer graphics pipelines like pipeline 120. Sometimes the multiple pipelines are coupled to a common system bus. For most modern applications, especially those involving stereoscopic computer graphics presentations, it is desirable for video controller 114 and CRT monitor 116 to comprise a progressive-scan rather than an interlaced-format system. Among the reasons for this are the flicker problems that are commonly associated with interlaced-format systems and the resolution reduction that is commonly inherent in stereoscopic interlaced-format applications.
FIG. 2 illustrates the logical organization of video controller 114. Video controller 114 cycles repeatedly through frame buffer 112 one scan line at a time. Raster scan generator 200 generates horizontal timing signals 202 and vertical timing signals 204, which in turn drive the raster scan in CRT monitor 116. Raster scan generator 200 also controls X address register 206 and Y address register 208, which together define what memory location will be specified by linear address generator 210. The memory addresses are generated in synchrony with the timing signals. Pixel data read from the accessed memory locations of frame buffer 112 are used as indices into look-up table 212. The contents of the corresponding locations within look-up table 212 are used to drive digital-to-analog converter ("DAC") 214. DAC 214 in turn produces the R, G and B beam intensity values used by CRT monitor 116.
It is known that raster scan generator 200 usually contains some form of video timing generator for producing horizontal timing signals 202 and vertical timing signals 204. Frequently, such video timing generators produce a V.sub.-- BLANK signal and a V.sub.-- SYNC signal as shown in FIG. 3, as well as an H.sub.-- BLANK signal and an H.sub.-- SYNC signal as shown in FIG. 4. CRT monitor 116 contains circuitry for generating the vertical and horizontal deflection signals shown in FIGS. 3 and 4, respectively, using the blank and sync signals as inputs. As can be seen in FIG. 3, the vertical deflection ramp signal retraces during VSYNC interval 300. In order to prevent the raster beam from being seen during vertical retrace, the R, G and B intensities are blanked during the retrace. Blanking actually begins at time 302 and ends at time 304. The interval between the beginning of blanking and the beginning of retrace is usually referred to as "vertical front porch" interval 306. The interval between the end of blanking and the beginning of active beam interval 310 is usually referred to as "vertical back porch" interval 308. For purposes of the discussion provided herein, the phrase "vertical refresh activity" will be used to denote any, all or some combination of the intervals 300, 306 and 308.
In the case of fully-programmable video timing generators, four counters might be used, one for each of the timing signals to be produced: V.sub.-- BLANK, V.sub.-- SYNC, H.sub.-- BLANK and H.sub.-- SYNC. In this manner, the relative lengths of all of the timing intervals may be controlled carefully by loading appropriate values into the counters and then decrementing the counters continuously. (In such an embodiment, a transition in a timing signal occurs whenever its corresponding counter reaches a zero count. The counter is then loaded with a second value corresponding to desired length of the next interval, and so on.) It is know that the intervals produced by such video timing generators may be altered by forcing a reset or load of the counter before the counter expires.
The horizontal timing of FIG. 4 is analogous to the vertical timing of FIG. 3. The horizontal deflection ramp signal retraces during HSYNC interval 400. In order to prevent the raster beam from being seen during horizontal retrace, the R, G and B intensities are blanked during the retrace. Blanking actually begins at time 402 and ends at time 404. The interval between the beginning of blanking and the beginning of retrace is usually referred to as "horizontal front porch" interval 406. The interval between the end of blanking and the beginning of active beam interval 410 is usually referred to as "horizontal back porch" interval 408. It should be noted, of course, that the horizontal cycle is much faster than the vertical cycle, commensurate with the number of lines in each frame. In fact, numerous horizontal retrace cycles may occur during one vertical front porch interval 306. Thus, to identify sub-intervals within vertical front porch interval 306, it is useful to speak in terms of the "first line of vertical front porch" and the "last line of vertical front porch."
For stereoscopic display systems, it is known to equip video controller 114 with left/right channel indicator 216. Left/right channel indicator 216 has a one-bit output for dictating which pixel data is to be used to drive CRT monitor 116 at any given moment. For example, in some stereoscopic implementations, left image data is stored in one memory area while right image data is stored in another memory area. In such implementations, the state of left/right channel indicator 216 is conventionally used by video controller 114 to determine which of the two memory areas should be displayed. The state of left/right channel indicator 216 is also typically used by eyewear 118 to determine which of the viewer's eyes is to be occluded at each moment. In prior art systems, left/right channel indicator 216 is a free-running oscillator; no automatic means is provided for synchronizing it with the left/right channel indicators of other computer graphics pipelines.
Moreover, in multi-display progressive-scan computer graphics systems, synchronization of vertical refresh cycles is complicated because no two crystals are the same. Therefore, no two video controllers have exactly the same clock frequency. The result for prior art progressive-scan multi-display systems is that, even if all video controllers were to begin a first vertical retrace at the same time, each would begin the next vertical retrace at a slightly different time. The systems would get further and further out of synchronization with each cycle.
By way of further background, it is known in interlaced-format environments to use a technique called "genlock." The genlock technique synchronizes vertical retrace, horizontal retrace and color burst phase and frequency among multiple interlaced-format display systems or sources such as those implementing the well-known NTSC composite video format. One by-product of using genlock in interlaced-format multi-display systems is that the timing of presentation for odd lines versus even lines is synchronized for all of the displays in the system. Thus, for stereoscopic multi-display systems that use an interlaced format in which the left channel is displayed on odd lines and the right channel is displayed on even lines, the genlock technique might be used to synchronize the display of left/right channels among the multiple displays, as well as to synchronize the vertical refresh cycles among the displays. As alluded to above, however, it is not desirable to use an interlaced format in stereoscopic applications because such a scheme inherently reduces image resolution by a factor of two. Moreover, the just-described form of genlock does not apply to progressive-scan systems.
It is therefore an object of the present invention to automatically synchronize the presentation of left and right channels by all of the computer graphics pipelines in a multi-display stereoscopic computer graphics system.
It is a further object of the present invention to automatically synchronize the vertical refresh cycles of each of the display devices in a multi-display stereoscopic computer graphics system.